The semiconductor memory business is a very competitive one in which cost is a function of, among other things, the bit density, the die size, and the device yield. The price commanded by a memory part is further impacted by the part's access speed and power consumption (particularly in the case of memory parts that are to be used in portable devices). For the highest bit density, a memory array having a two feature square (2F2) storage cell size is the most efficient (ignoring multiple bit per cell devices). A diode cross-point memory structure achieves this density. To interface to such a memory structure, row and column decoder circuits must be incorporated and, to minimize the die size, a high ratio of memory circuitry to peripheral circuitry must be achieved which requires that the decoder circuitry must be efficiently designed.
Array decoders based on diode decoding circuits are very efficient. Device yield must be maximized and, since redundant circuitry increases both die size and test (repair) costs, error correcting (ECC) techniques can be utilized in their place. Furthermore, to better support ECC efficiency in the case of defects in word lines and bit lines, a diagonal access technique (as is disclosed in U.S. Pat. No. 7,149,394 to Shepard, the entire disclosure of which is hereby incorporated by reference herein) can be employed which requires the word-line and bit-line access to advance while a data block is accessed. A trade-off is often an issue with speed and power consumption. Many memory decoders utilize a tree decoding structure to save power and reduce die size, but this can introduce decoding delays as the address decoding must be decoded in a first stage and be allowed to stabilize before decoding in a second or subsequent stage. This approach saves power by not energizing portions of the decoder outside of the tree branch being selected.
Many types of non-volatile storage arrays exist in the prior art and the array lines in most of these arrays are connected with decoder driver circuits. Often, as can be found in the prior art, to enable the drivers to be fabricated with half the pitch as the array lines themselves, these driver circuits are placed on both sides of the array with alternate array lines exiting the array on opposite sides. A drawback to this approach is that the decoder circuitry is duplicated to some degree on both sides of the array. If the decode circuitry is not very efficient, this duplication will significantly increase the die size and cost.